Transistor pulse memory circuits



July 7, 1953 J. B. GEHMAN 2,644,892

TRANSISTOR PULSE MEMORY CIRCUITS v med June 2, 1952 25 Uff JJ /4 .m0/mf'0F j /MOafP//zsfs ff @WWW fz Ufff f zd Z h(Ef/6 z5 JMW- T z/ 1717.1, ff,7 l www 50a/76E' 0F /MZIaMrM/ "X24 PSES v ATTORNEY Patented July 7,1953 2,644,892 n TRANSISTOR PULSE MEMORY CIRCUITS John B. Gehman,Haddoneld, N. J yassigner to Radio Corporation of America, a corporationof Delaware Application June 2, 1952, Serial No. 291,176

15 Claims.

This invention relates generally to memory circuits, and particularlyrelates to a systemutilizing a current multiplication transistor forstoring an electrical pulse and determining Within a predeterminedinterval oi time Whether a pulse has previously been stored or not.

Memory circuits find Wide application, for example, in many types ofelectronic computers. Thus some computers require means for storinginformation which will later be referred to by the computer to completea calculation. In some types of computers memory is provided by means ofa magnetic tape which stores the desired information. Frequently, it isnecessary to obtain a plurality of pulses simultaneously from themagnetic tape, each pulse representing information. These pulses usuallymust be fed simultaneously to the computer. However, the magnetic tapemay become mechanically stretched or askew or it may not be feasible toderive or pick up all the pulses simultaneously from the tape. In thatcase, an additional memory circuit may be required into which thevarious pulses derived from the tape are fed in succession for temporarystorage and from which they may be derived at will simultaneously.

It is an object of the present invention, therefore, to provide pulsememory circuits utilizing transistors.

Another object of the invention is to provide a transistor circuit whichwill indicate Whether or not a pulse has previously been applied to thecircuit Within a predetermined relatively long interval of time. y

A further object of the invention is to provide a memory circuitincluding a current multiplicatien transistor which will develop anoutput pulse of predetermined fixed amplitude in response to aninterrogating pulse when an input pulse has previously been appliedwithin a predetermined interval of time to the circuit.

Stillanother Object of the invention is to pro- Vide a memory circuit ofthe type previously referred to which might be termed an inhibitedcircuit and which will develop van output pulse of a relatively smallamplitude in response to an interrogating pulse occurring within apredetermined interval of time after the occurrence of an input pulse.

The pulse memory circuit of the present invention may becensideredanimprovement over the semi-conductor pulse memory circuits disclosedand claimed in applicants copending application :tiled concurrentlyherewith, Serial No. 219,177, and assigned tothe assignee ofthisapythrough the emitter.

plication. However, the pulse memory circuit of the present inventionprovides a memory time which is several hundred times as long as that ofthe memory circuit disclosed in the copending application.

The pulse memory circuit of the present invention comprises a currentmultiplication'transister, that is, a transistor having a ratio ofshortcircuit collector current increments to emitter currentincrementsvwhich is greater than unity. Such a current multiplicationtransistor may be connectedin a network in such a manner that thecircuit is normally not regenerative but is brought or carried into theregenerative state by the application of an input pulse to the circuit.The circuit then remains in its regenerative state for a predeterminedextended period of time. Hence, if an interrogating pulse is applied tothe circuit within that interval of time, an output pulse of relativelylarge amplitude is obtained.

It is also feasible to operate the circuit of the' invention in such amanner that the circuit is normally in its regenerative state and iscarried out of the regenerative state by the application of an inputpulse for a predetermined interval of time. Such a circuit might becalled an inhibited circuit .because it inhibits the development of alarge output pulse in response to an interrogating pulse occurringWithin a predetermined interval of time after the occurrence of theinput pulse.

The transistor of the present invention is provided with an impedanceelement which effectively ceuples the emitter and collector electrodes.If such a circuit is energized in a conventional manner, a bistable orflip-liep circuit will result. Such bistable circuits have beendisclosed and claimed in the patent to Eberhard 2,533,001. 'I'heimpedance element which couples the emitter and collector may either beprovided between the base and ground or it may connect directly theemitter to the collector.

In accordance with the present invention, it is not necessary to applyany bias potential to the transistor. Instead, input pulses are appliedbetween emitter and base which may, for example, bias emitter and basein the forward direction. If We assume that the semi-conducting body orcrystal of the transistor is of the N type, the input pulse may developa voltage of positive polarity which will inject holes into the crystalHowever, if the transistor should include a crystal of the P type, thepulses .applied to the Lemitter may develop a voltagev 3 of negativepolarity which will inject electrons into the crystal.

In accordance with the present invention, these pulses are appliedthrough a transformer or inductor which preferably is a wide bandtransformer. Assuming again that the transistor includes an N typecrystal, a large negative pulse may be impressed on the transformer.Upon the occurrence of the trailing edge of the input pulse thetransformer will develop a small positive potential which will exist foran appreciable period of time. During the existence of this positivepotential, the transistor network is rendered regenerative and willdevelop a large output pulse in response to an interrogating pulseapplied between collector and base.

Alternatively, for providing an inhibited circuit the transistor isadjusted to be normally in the regenerative state and a large positivepulse is applied to the input transformer. Consequently, upon theoccurrence of the trailing edge of the pulse, a small negative potentialwill be developed across the transformer which carries the transistornetwork out of the regenerative state as long as the negative voltageexists at the emitter. Consequently, if an interrogating pulse isapplied to the collector during a predetermined interval of time afterthe occurrence of the ltrailing edge of the input pulse, a relativelysmall output pulse only is developed across the collector load.

The novel features that are considered characteristic of this inventionare set forth with particularity in the appended claims. The inventionitself, however, both as to its organization and method of operation, aswell as additional objects and advantages thereof, will best beunderstood from the following description when read in connection withthe accompanying drawing, in which:

Figure 1 is a circuit diagram of a pulseV memory circuit embodying thepresent invention;

Figure 2 is a graph illustrating the input and output voltages obtainedfrom the circuit of Figure l plotted as a function of time;

Figure 3 is a circuit diagram of a modified pulse memory circuit inaccordance with the invention;

Figure 4 is a circuit diagram of a preferred pulse memory circuit inaccordance with the present invention which may be operated as aninhibited circuit;

Figure v5 is a graph illustrating the input and output voltages derivedfrom the inhibited circuit of Figure 4 plotted as a function of time;and

Figure 6 is a circuit diagram of a multiple pulse storage system inVaccordance with the present invention.

Referring now to the drawing in which like elements are designated bythe same reference numerals throughout the figures and particularly toFigure 1, there is illustrated a pulse memory circuit comprising atransistor I0 indicated schematically. The transistor I0 includes a`semi-conducting body II, a base electrode I2, an emitter electrode I3and a collector electrode I4 in contact with the semi-conducting body orcrystal I I The transistor I0 may be of the point contact type, that is,emitter I3 and collector I4 may be in rectifying contact with thecrystal I I. However, in any case, the transistor I0 should be a currentmultiplication transistor where the collector current increments arelarger than the corresponding emitter current increments.

An external network interconnects the electrodes I2-III of thetransistor with a common junction point such as ground. Thus, the baseI2 may be grounded through a base resistor I5 which may be adjustable asshown. Emitter I3 is grounded through the winding I5 of inputtransformer II having a primary winding I8. Collector I4 may be groundedthrough an output load resistor 20 connected in series with thesecondary winding 2| of a transformer 22 including a primary winding 23.By means of the transformer 22 interrogating pulses obtained from source24 are applied to the transistor as will be more fully explainedhereinafter.

Input pulses developed by source 25 are imf pressed on the primaryWinding I8 of input transformer I'I in a manner which will be more fullydiscussed hereinafter.

It Will be noted that no sources of direct current voltages are shownnor are any required for the memory circuit of the invention. It willalso be noted that no capacitors are provided for storing direct currentvoltages. If the transistor network described so far were operated inthe conventional manner by applying a forward bias voltage to theemitter i3 and a reverse bias voltage to the collector I4 with respectto the base I2, a regenerative amplier or bistable circuit would beobtained. Such a circuit has been disclosed in Figure 3 of the Eberhardpatent previously referred to.

In accordance with the present invention, input pulses indicated at 21and derived from source 25 are impressed between emitter I3 and base I2through input transformer Il. The input pulse 21 as impressed on emitterI3 is of negative polarity and biases the emitter I3 and base I2 in thereverse direction provided the crystal II is of the N type as indicatedby the transistor symbol. The arrow representing emitter I3 pointstoward crystal II to indicate that holes are injected into an N typecrystal; if the arrow representing the emitter points away from thecrystal II, a P type crystal is indicated and the holes will move fromthe crystal to the emitter. If the semi-conducting crystal iI were ofthe P type, the polarity of the input pulses 25 should be reversed toobtain the same type of operation.

As already explained, the input pulses are developed by source 25 andimpressed on the input transformer I 'I so as to obtain a negative pulse26 which is developed across secondary winding I8. The transformer IIpreferably is a wide band transformer. Accordingly, the inductivecoupling between the primary winding I8 and the secondary winding I6should be large. In other words, the leakage reactance of thetransformer should be low. The inductive coupling will control thehigh-frequency response of the transformer. Furthermore, the inductanceof both the primary winding I8 and the secondary winding I6 should belarge to obtain a good low frequency response.

The voltage developed across the secondary winding I6 in response to aninput pulse is illustrated by curve 21 of Figure 2. The pulse width isindicated by t1 and may, for example, amount to a few microseconds. Uponthe occurrence of the trailing edge of the input pulse indicated at 28,a small positive voltage indicated by curve portion 30 is developedacross the secondary winding I6. For example, the amplitude of the inputpulse 2'I may be 50 volts and the amplitude of the positive voltageindicated at 30 may amount to +25 to 50 mllivolts. The magnitude of thepositive voltage represented by curve has been exaggerated in Figure 2.f

'As long as the positive voltage 3U exists, that is, during the intervalof time indicated at tz portion Y3l) the circuit of Figure 1 will beinits regenerative During this ent-ire interval of time, holes` state. areinjected through the emitter I3 into'- the crystal 'II and consequentlythe circuit remains in its regenerative:state.'

The time constant' of the circuit of Figure 1,

that is, of the circuit including secondary winding I6, emitter I3, baseI2 and base resistor I5 is essentially determined by AL/R, wherein L isthe inductance of secondary winding I6 and R is the resistance whichappears lookinginto emitter I3. More correctly t=KL/R, where-K is aconstant determined by the adjustment of the circuit will be explainedhereinafter. IActually,

vforward direction is applied between emitter and base, for example, thepositive voltage 30.

R2 is of the order of 100 ohms and accordingly lf2/t1 is approximately1,000. By'way of example, the time t1 may be of the order. of 5 to 7microseconds and tz may be as large as 7,000 microseconds. is thestorage time, depends upon the value of Lthe inductanceof secondarywinding I6 and upon R2 which depends upon l the particular transistor.The constant K is determined by the state of regeneration of the circut,that is, how readily the circuit can be carried into the regenerativestate.

As explained hereinbefore, the input transformerY IIpreferably is a wideband transformer. It will now be seen that the large value of theinductance of the secondary windingV I6 increases the storage time anddetermines the low frequency response of the transformer. On the otherhand, the high magnetic coupling between primary winding I8 andsecondary winding I6 which is equivalent to a low leakage reactancedetermines the high frequency response of the transformer and hence,makes itpossible to impress a relatively narrow input pulse 21 on thetransformer. The transformer `I1 r'nay be replaced by the inductor I6 onwhich the input pulse 21 is impressed. f

Further in accordance with the'pres'ent invention, the transistor memoryycircuit may be interrogated by means of 'interrogating pulses developedby the source 2 4 and impressedV on transformer 22. As illustrated at 32the interrogating pulses appear with negativepolarity at' the collectorI 4. During the time tithe transistor memory circuit of the inventioni's'carried into its, regenerative state by the positive lvoltage 30 andconsequently whenan interrogatingpulse 32 is impressed between collectorI4 and base I2, a comparatively large output pulse indicated at 33 inFigure 2 is developed across theload resistor 20. Thisoutput pulsefmaybe obtained from output terminals 34. However, when the interrogatingpulse 32 is applied to the circuit outside of the time t2, acomparatively small output pulse indicated at 35 in Figure 2 isdeveloped Of course, the actual value of tzwhich which has been shown tobe adjustable.

sistance ofthe base resistor I5 should be adjust- 6 v across the loadresistor L20. The voltage kick 36 shown in Figure 2 which appears acrossload resistor 20 occurs in response to the applied input pulse `2`Ifeedingthrough the transistor.

Thus, the positive voltage 30 developed .across the secondary windingkI6 of the input transformer carries the transistor'into a regenerativestate where it is capable of providing alarge co1- lector f current inresponse to an interrogating pulse being applied during thepredetermined interval of time t2. During the time interval tzr y thetransistor is conditioned to` develop a comparatively large output pulsesuch as shown at 33 in response to, an interrogating pulse 32. However,only av small output pulse 35 is obtained if the interrogating pu1se'32occurs ata time later than or prior to tz. Hence, the pulse memorycircuit of the invention isable to determine whether orr not an inputpulse has previously been applied thereto'within a predeterminedinterval of time which may be of the order of 7,000 microseconds. v

It is to be understood that itis also feasible to apply bias voltages toeither the collector or to vthe emitter or to both in the conventionalmanner.

These bias voltages, however, should be so small that the transistornormally is not `in the regenerative state but can only be carried intoits regenerative state by the application of an input pulse 2'I whichsubsequently develops a positive voltage as indicated at 30. Themagnitude of the bias voltages-which may be applied will depend upon theindividual transistor and on the resistance o-f the base resistor I5 Thereed so that the positive voltage 30 will bring the transistor into itsregenerative state and so that the transistor will remain in 'itsregenerative state until the positive voltage 30 substantiallydisappears. Careshould be taken by adjusting the bias voltages if anyare applied, and by adjusting the resistance of base resistor I5 softhatthe transistor will Vnot be in Athe regenerative state in the absence ofan input pulse orafter the predetermined time interval t2 has elapsed..

As illustrated in Figure 1 ofthe Eberhard patent above'referred to it isalso feasible to obtain a bistable transistor circuit or regenerativeamplier by connecting a resistor directly. between emitter andcollector. Such al regenerative transistor amplier circuit may beutilized in the pulse memorycircuit of the invention as shown in Figure3. A resistor 31 which may beadjustable as shown, is connected directlybetween emitter I3 and collector I4. The input pulses are applied to theterminals 25 in the manner previously described and the secondarywinding I6 ofV the input transformer is connected directly betweenemitter I3 and base I2. The interrogating pulse generator 24 may becoupled'by coupling capacitor 38 across a load resistor 40 seriallyconnected with the primary winding of 'an output transformer 4Ibetweenkbase I2 and collector I4.

y The operationiof vthe circuit of FigureB is essentially the same asthat ofthe circuit of Figure 1.Y kBy the rapplication of a negativeinput n f pulse 21, a positive voltage is eventually applied to theemitter I3 Which carrie'sthe circuit into its regenerativestate. Again acomparatively .largeoutput pulse is developed across the outputAtransformer 4I which maybe obtainedfrom outfput terminals y34, inresponse to an interrogating pulse 32 appliedzduring the ytime yt2.

In the circuits of Figures 1 and 3 the external emitter' resistance mustbe low. In other Words, the resistance of the secondary winding I6should be small. The value of the base resistor I in Figure 1 may be1,000 ohms or less and the output load resistor may have a resistance ofbetween 100 and 1000 ohms.

The circuit of Figure 4 to which reference is now made is a modificationof the memory circuit of Figure 1. The circuit of Figure 4 is apreferred embodiment of the present invention. The secondary winding I6of the input transformer I1 is again connected in series with the baseresistor I5 between base I'2 and emitter I3. The input pulses areapplied to the input terminals connected to the primary winding I8 ofinput transformer Il. The output load resistor 20 is connected in serieswith the secondary winding 2| of the transformer 22 between collector I4and emitter I3. The interrogating pulses 32 may be impressed on theinput terminals 24 connected to the primary winding 23 of transformer22.

The circuit of Figure 4 may be operated in the same manner as is thecircuit of Figure 1. How'- ever, it is also feasible to operate thecircuit of Figure 4 as well as those of Figures 1 and 3 in such a manneras to obtain an inhibited circuit. To this end, the circuit of Figure 4is adjusted in such a manner as to be normally f regenerative, that isythe circuit is regenerative in the absence of an input pulse. In otherwords, the circuit is adjusted in the manner previously explained byadjustment, for exampleY of the base resistor I5 and of the biasvoltages if any Y are applied, so that, in the absence of an inputpulse, a comparatively large output pulse is developed across the loadresistor 20 in response to an interrogating pulse 32.

By the application of an input pulse between l emitter I3 and base I2 isis possible to carry the circuit of Figure 4 out of the regenerativestate so that a comparatively small output pulse is obtained in responseto an interrogating pulse. This mode of operation may be explained byreference to Figure 5. A positive input pulse is now applied across thesecondaryV Winding I6 of the input transformer. In the same manner aspreviously explained, after the occurrence of the trailing edge 46 ofthe input pulse, a negative voltage indicated at 41 is developed acrossthe secondary Winding I6 which is impressed on the emitter I3.

This negative voltage 41 will exist for an interval of time t2 which maybe calculated in the o same manner as previously explained. The timeconstant t1 is now determined by K11/R2, where R2 is the resistancewhich appears looking into emitter I3 When the emitter to base path isbiased in the forward direction. The time interval t2 is determined byKL/Rr, where R1 is the resistance which appears looking into the emitterwhen a negative or reverse voltage is impressed between emitter andbase. Consequently, the time interval t2 will be much shorter than whenthe transistor is operated so that a positive voltage is applied to theemitter. However, since tg=KL/R1, it is possible by careful adjustmentof the circuit to increase t2, the inhibiting memory, by the factor K.

It should be noted that during time interval t3 the transistor remainsin its regenerative state. This mode of operation of the memory circuitof the invention has been explained in applicants copending applicationpreviously referred to.

Thus, when a positive input pulse 41 is applied to the emitter, holesare injected through emitter I3 into the crystal I I. These holes willexist for a certain length of time which depends on the geometry of thetransistor and on the properties of the crystal II. After this intervalof time t3, which may be of the order of 15 microseconds, the holes aredissipated either by diffusion or migration or by recombination withelectrons.

Consequently, when an interrogating pulse is applied during the timeinterval t3, a large output pulse indicated at 5U is developed acrossthe load resistor 20. A similarly large output pulse 5I is obtained whenthe interrogating pulse is applied outside of the time interval t2.However, if the interrogating pulse is applied during the time intervalt4, that is after the termination of the interval t3 and before thetermination of the interval t2, a comparatively small output pulse 52 isdeveloped across the load resistor. Accordingly, if the circuit ofFigure 4 is operated in the manner just outlined, the circuit willinhibit the development of a large output pulse across the load resistorduring a predetermined interval of time t4. It will be obvious that thecircuits of Figures 1 and 3 may also be operated in the same manner.

As illustrated in Figure 6, it is also feasible to utilize the memorycircuit of the invention for storing a plurality of input signals in acorresponding number of memory circuits and to interrogate all thememory circuits simultaneously. By way of example four input signalshave been shown in Figure 6, each of which is applied to a separatememory circuit of the type illustrated in Figure 1. The elements of thecircuits to which input signals Nos. 2, 3 and 4 are applied have beendesignated by corresponding reference numerals provided with a prime,double prime and triple prime respectively. The junction points betweenbase resistor I5 and secondary winding I6, base resistor I5 andsecondary winding I5 and so on are connected together to one terminal ofthe secondary winding 2|, the other terminal of which is grounded. Thus,the interrogating pulses are applied simultaneously through secondarywinding 2I between collector I4 and base I2 or collector I4 and base I2and so on of all the circuits. The output resistors 20, 20' and so onhave one terminal connected to their respective collector I4, I4 and soon while the other terminal is grounded.

The multiple channel storage circuit of Figure 6 may, for example, beutilized to feed separate input signals either simultaneously or insuccession to the inputs Nos. I, 2 and so on through transformers Il,I'I and so forth. In response to an interrogating pulse being applied toall the circuits simultaneously the output signals obtained from outputterminals 34, 34 and so on will occur simultaneously with uniformamplitudes. Thus, the signals or pulses stored on a magnetic tape may beimpressed on the input terminals of the channel storage circuit fromwhich they are derived simultaneously in response to an interrogatingpulse. It is also feasible to impress the input signals simultaneouslyon the inputs Nos. I, 2 and to interrogate each circuit individually byproviding separate transformers 22 to each circuit to derive the storedsignals in succession.

There have thus been disclosed pulse memory circuits which utilize acurrent multiplication transistor. The transistors may be operatedwithout applying any direct current voltages. The

V,cilrouit is able to determinewhether or not an input pulse lhaspreviously been impressed thereon within e a predetermined interval of.tiineiwhieh may bei ofthe malerei-.7,000 microseconds-` Itis alsofeasible to operate the memory circuit ofthe inventionas an inhibitedcircuitwhich'willprevent the development of .a large output pulse 'inresponse toan interrogating pulse.` Furthermore, it is feasible toprovide. multiple channel lstorage of `input 4pulses applied for storagein succession and to derive the output 4signals lsiinultaneousllyinresponse to an interrogating. pulse.

What isvclaimed is: Y l. A pulse memory circuit comprising a currentmultiplication transistor including a semi-con-A ducting` body, a baseelectrode, an emitter electrode and a collector electrode in contactwith said body; a rst impedance element eiiectively coupling saidemitter andcollector electrodes, an

input inductor eliectively connected between said emitter and baseelectrodes, and providing a time polarity to bias said collector andbase electrodes in the reverse direction, whereby an output pulse ofpredetermined amplitude is developedacross said second impedance elementin response to an interrogating pulse occurring substantially within theduration of said voltage of opposite polarity and an'output pulse of adifferent amplitude is developed across said second impedance element inresponse to an interrogating pulse occurring at a time outside of theduration of said voltage of opposite polarity. 3

2. A pulse memory circuit comprising a current multiplication transistorincluding a semiconducting body, a base electrode, an emitter electrodeand a collector electrode in contact with said body, a first impedanceelement effectively coupling said emitter and collector electrodes, aninput inductor eiiectively connected between said emitter and baseelectrodes, and providing a time constant network together with. theresistance which appears looking into said emitter, an output secondimpedance element effectively connected between said collector and baseelectrodes, means for applying an input pulse to said inductor having apolarity to bias said emitter and base electrodes in the reversedirection, whereupon a voltage of opposite polarity and smalleramplitude is developed across said inductor after the occurrence of thetrailing edge of said input pulse, said voltage of opposite polaritybiasing said emitter and base electrodes in the forward direc-V tion,said rst impedance element being adjusted so as to render saidtransistor regenerative for the duration of said voltage of oppositepolarity, and means for applying interrogating-pulses between saidcollector and base electrodes of a polarity to bias said collector andbase'electrodes in the reverse direction, whereby an output pulse ofpredetermined large amplitude is developed' across said second impedanceelement inresponse to an interrogating pulse occurring within theduration of said voltage of opposite polarity and an output pulse ofsmall amplitude is developed is relatively large.

kacross said .Second impedance element in response to aninterrogatingpulse occurring at a timeoutside of the duration 0I Saidvcltae' Qf loppofstepolarity.

` 3. A pulsememory circuit comprising a current *inputr transformerhaving a secondary winding efffectively connected between said emitterand base electrodes, anfd providing a time constant network togetherwihlthe resistance whichap'pears look-v ing into said` emitter, anoutput -second impedance element effectively connected between saidcollector and base electrodes, means for 'applying' yan input pulse torsaid input transformer having a polarity to bias said emitter and baseelectrodes in the reverse direction, whereupon a voltage 'of oppositepolarity and smaller amplitude yis'developed across said secondarywinding' after the occurrence lof the trailing edge of said input'pulse,said voltage of opposite polarity biasing said lemitter and baseelectrodes in the forward direction, said nrst impedance element beingadjusted so as to render said transistorregenerative vfor the durationof said voltage of opposite polarity, and means for applyinginterrogating ypulsesbetween said collector and base electrodes of apolarity to bias said collector and base electrodes in the reversedirection, said pulses being thevsole sources of potential of saidtransistor, whereby an output pulse of predetermined largeainplitude isdeveloped across said second impedance element in response toaninterrogating pulse occurring Within the duration of said voltage ofopposite polarity and an output pulse of small amv plitude is developedacross said second impedance element in response to an interrogatingpulse occurring at a'time outside ofthe duration of said voltage ofopposite polarity. .-f

4. A'pul'se lmemory circuit as defined in claiin13 wherein said inputtransformerlis a'wideband transformer having arelatively high magneticAcoupling between its primary and secondary windings, whereby the leakagereactance is low, and wherein the inductance of said secondary winding5. A pulse memory as defined in claim k3 in said'frst impedance elementis a resistor. 1

6. A pulse memory as defined in claim -3 wherein said first impedance`element is connected directly between said emitter and collector lelec-7. Apulse memory circuit as defined in claimv3 wherein said firstimpedance element is connected serially with-said secondaryfwindingbetweensaid base and emitter electrodes; u y

8. A pulse memory circuit comprisingfa current multiplication transistorincluding a semi-con-v ducting body, a base'electrode, an emitter elecftrode and a collector electrode in contact with said body,`a firstimpedance element andan input inductor forming a first seriesconnectionaand effectively connected between said emitter and baseelectrodes, and providing a time constant network together with the`resistance which appears looking into'said emitter, an output secondimpedance element, vand. a third impedance element forming a secondseries connection and effectively connected between said collectorelectrode,fand said first series connection, meansffor applying aninputpulsey to rsaid inductor having a polarity to bias said emitter and baseelectrodes in the reverse wheredirection,whereupon a voltage of oppositepolarity and smaller amplitude is developed across said inductor afterthe occurrence of the' trailing edge of said input pulse, said voltageof opposite polarity biasing said emitter and base electrodes in theforward direction, said iirst impedance element being adjusted so as torender said transistor re.- generative for the duration of said voltageof opposite polarity, and means for applying interrogating pulses tosaid third impedance element of a polarity to bias said collector andbase electrodes in the reverse direction, said pulses being the solesources of potential of said transistor, whereby an output pulse ofpredetermined large amplitude is developed across said second 1mpedanceelement in response to an interrogating pulse occurring within theduration of said voltage of opposite polarity and an output pulse ofsmall amplitude is developed across said second impedance element inresponse pulse occurring at a time outside of the duration of saidvoltage of opposite polarity.

9. A pulse memory circuit as defined in claim 8 wherein said firstimpedance element is a resistor.

10. A pulse memory circuit wherein said second series connection isconnected between said collector electrode and the junction between saidfirst impedance element and said input inductor.

ll. A pulse memory circuit as dened in claim 8 wherein said secondseries connection is connected directly between said collector andemitter electrodes.

12. A multiple pulse storage system comprising a plurality of pulsememory circuits, each including a current multiplication transistorhaving a semi-conducting body, a base electrode, an emitter electrodeand a collector electrode in contact with said body, a rst impedanceelement effectively coupling said emitter and collector input induotoreiectively connected between said emitter and base electrodes, andproviding a time constant network together with the resistance Y whichappears looking into said emitter, and an output second impedanceelement eirectively connected between said collector and a point ofsubstantially fixed potential; means for applying individually an inputpulse of predetermined polarity to each of said inductors whereby avoltage of opposite polarity and smaller amplitude is developed acrosseach inductor after the occurrence of the trailing edge of said inputpulse, and means for applying simultaneously an interrogating pulsebetween the collector and base electrodes of each transistor of apolarity to bias each collector and its associated base electrode in thereverse direction, whereby an output pulse of predetermined amplitude isdeveloped across each of said second impedance elements in response toan interrogating pulse.

13. A multiple pulse storage system comprising a plurality of pulsememory circuits, each including a current multiplication transistorhaving a semi-conducting body, a base electrode, an emitter electrodeand a collector electrode in contact with said body, a first impedanceelement eiiectively coupling said emitter and collector electrodes, aninput inductor effectively connected between said emitter and baseelectrodes, and providing a time constant network together with theresistance which appears looking into said emitter, and an output secondimpedance element effectively connected between said-collector and apoint of substantially fixed potential; means for applying individuallyto an interrogating as dened in lclaim 8 electrodes, an 1 and at randoman inputV pulse to each of said inductors to bias the associated'emitterand base electrodes in the reverse direction whereby a voltage ofopposite polarity and smaller amplitude is developed across eachinductor after the occurrence of the trailing edge of said input -pulseto bias said associated emitter and base electrodes in the forwarddirection and means for applying simultaneously an interrogating pulsebetween the collector and base electrodes of each transistor of apolarity to bias each collector and associated base electrodes in thereverse direction, whereby an output pulse of predetermined largeamplitude is developed across each of said second impedance elements inresponse to an interrogating pulse occurring within a predeterminedinterval of time from said input pulses.

14. An inhibited pulse memory circuit comprising a currentmultiplication transistor including a semi-conducting body, a baseelectrode, an emitter electrode and a collector electrode in contactwith said body, a rst impedance element effectively coupling saidemitter and collector electrodes, an input inductor effectivelyconnected between said emitter and base electrodes, and providing a timeconstant network together with the resistance which appears looking intosaid emitter, means for applying an input pulse to said input inductorhaving a polarity to bias said emitter and base electrodes in theforward direction, whereupon a voltage of opposite polarity and smaller'amplitude is developed across said inductor after the occurrence of thetrailing edge of said input pulse to bias said emitter and baseelectrodes in the reverse direction, said first impedance element beingadjusted so as to render said transistor regenerative for the durationoi' said input pulse and non-regenerative Afor a predetermined portionof the duration of said voltage of opposite polarity, and means forapplying interrogating pulses between collector and base electrodes of apolarity to bias said collector and base electrodes in the reversedirection, whereby an output pulse oi predetermined small amplitude isdeveloped across said second impedance element in response to aninterrogating pulse occurring substantially within said predeterminedportion of the duration o said Voltage or said opposite polarity and anoutput pulse of large amplitude is developed across said secondimpedance element in response to an interrogating pulse occurringsubstantially outside of the duration of said voltage of oppositepolarity.

l5. An inhibited pulse memory circuit comprising a currentmultiplication transistor including a semi-conducting body, a baseelectrode, an emitter electrode and a collector electrode in contactwith said body, a rst impedance element eii'ectively coupling saidemitter and collector electrodes, an input transformer having asecondary winding effectively connected between said emitter and baseelectrodes and providing a time constant network together with theresistance which appears looking into said emitter, means for applyingan input pulse to said transformer having a polarity to bias saidemitter and base electrodes in the forward direction, whereupon avoltageof opposite polarity and smaller amplitude is developed across saidsecondary winding after the occurrence of the trailing edge of saidinput pulse to bias said emitter and base electrodes in the reversedirection, said nrst impedance element being adjusted so as to rendersaid transistor regenerative for the duration of said input pulse andnon-regenerative for a pre- 13 determined period of time beginning apredetermined instant after the occurrence of said trailing edge and forthe remainder of the duration of said voltage of opposite polarity, andmeans for applying interrogating pulses between collector and baseelectrodes of a polarity to bias the collector and base electrodes inthe reverse direction, said pulses being the sole sources of potentialof transistors, whereby an output pulse of predetermined small amplitudeis developed 10 across said second impedance element in response to aninterrogating pulse occurring substantially during said predeterminedperiod of time and an output pulse of large amplitude is developedacross said second impedance element in response to an interrogatingpulse occurring substantially outside of said predetermined period oftime.

JOHN B. GEHMAN.

14 References Cited in the file of this patent UNITED STATES PATENTSNumber Name Date 2,569,345v yShea Sept. 25, 1951 2,591,961 Moore Apr. 8,1952 2,594,449 Kircher Apr. 29, 1952 2,620,448 Wallace Dec. 2,. 19522,622,211 Trent Dec. 16, 1952 2,623,170 Dickinson Dec. 23, 19522,627,039 MacWilliams Jan. 27, 1953 OTHER REFERENCES The Transister.YBell Telephone Labs., pp. 627- Computers Using Transisters. by J. H.

Felker.

Electrical Engr., pp. 1103-1108, December 1952.

